Fundamental Algorithms for Physical Design Planning of VLSI

He brought me into the field of VLSI CAD. His encouragement and guidance has been a tremendous help throughout my PhD study. The fruitful discussions with him have bloomed many unexpected and stimulating thoughts. Also the criticism from him has led to a higher quality of research work. discussion. Special thanks are due to Ruiqi Tian and Hua Xiang, who help me a lot in completing this dissertation work. All my friends have paid me joyful time for so many years. I thank them all, although I can only mention a few here. Among them are Xiang Feng, Lei Gao, I also take this opportunity to express my greatest gratitude to my family and the hidden people behind this research work. Their love has always been the constant source of my energy and thought. Rapid advances in semiconductor technologies have led to a dramatic increase in the complexity of VLSI circuits. With fabrication technology entering deep submi-cron era, devices are scaled down, more functionalities are integrated into one chip, and chips run at higher clock frequencies. Handling the extremely large designs with ever-increasing clock rates, while reducing design turnaround time and ensuring timing convergence, is exhausting the capabilities of traditional design tools. Thus careful up-front design planning, analyzing physical implementation effects before the actual place-and-route, is essential in designing today's multi-million and future's billion gate ICs. We study several fundamental problems of VLSI physical design planning in this dissertation. In floorplanning, we develop a floorplanner FAST-SP based on sequence pair floorplan representation. A new approach is proposed to evaluate a sequence pair based on computing longest common subsequence in a pair of weighted se-obtain the best results ever reported in the literature with significantly less runtime. Placement constraints are important in floorplanning. We consider fixed-frame floorplanning and extend FAST-SP to handle placement constraints such as pre-placed constraint, range constraint, boundary constraint, abutment constraint, alignment constraint, rectilinear shape constraint, and performance constraint. We propose a uniform method to deal with all these constraints. Buffer planning is a key component in design planning. We present a new approach to buffer planning based on network flow computation. Our algorithm optimally solves the problem of inserting maximum number of buffers into the free space between the circuit blocks with minimum total cost in polynomial time. Buffered routing tree construction is essential in wire planning. We consider the problem of constructing routing trees with simultaneous …